1. Field of the Invention
The present invention relates to the field of automatic design automation (EDA) technology. More specifically, the present invention relates to an improvement to computer implemented fitting programs that are used to automatically place and route resources of a programmable logic device with respect to a given programmable logic device (PLD) design. The improvements include proactive debugging of fitting problems.
2. Related Art
Electronic design automation (EDA) systems allow designers of integrated circuit (IC) devices, and also designers who want to implement a design on a programmable logic device (PLD), to use high level language (HDL) descriptions to represent their IC or PLD designs (e.g., hardware designs) at an abstract or high level. In addition to HDL, the design descriptors can also include any method of representing a hardware design, such as schematic, combination and others. These schematic or HDL descriptions are then synthesized by computer implemented processes that generate technology dependent descriptions of the IC or PLD design called xe2x80x9cnetlists.xe2x80x9d The PLD chip can be a programmable logic device, such as a complex programmable logic device (CPLD), or a field programmable logic array (FPGA). These programmable logic devices contain generic functional modules that can be electrically coupled together and programmed to perform certain functions and generate specific signals such that an IC or PLD design can be realized in hardware.
Part of the design process for programmable logic devices includes processes called xe2x80x9cfitting.xe2x80x9d Fitting processes are used to fit the IC or PLD design to the programmable logic device and these processes include determining the PLD resources that are used and also determining the required timing. Fitting processes are also commonly called xe2x80x9cplace and routexe2x80x9d processes. The end result of fitting, with respect to CPLDs, is a programming file, e.g., JEDEC file or bitstream file, for the CPLD device. When programmed using the programming file, the CPLD implements the IC or PLD design in hardware.
All CPLDs have architectural limitations which cannot be violated or the IC or PLD design will not successfully fit to the CPLD device. If architectural limitations are violated, then fitting problems occur within the fitting process. However, conventional fitter software frequently does not give an accurate description as to the root cause of any discovered fitting programs and often does not give any information as to the cause or reason for fitting problems. This can be very frustrating for the designer trying to debug an IC or PLD design that fails to fit to particular CPLD device.
As a result, when faced with troublesome fitting programs, it is often the case that an IC or PLD designer contacts an applications hotline engineer that is familiar with the CPLD device. The applications hotline engineer then examines the IC or PLD design and manually applies debugging processes to address any fitting problems and manually suggests possible fixes. However, this approach slows the user""s design cycle because the design cycle is typically placed on hold while the IC or PLD designers wait for the applications engineer to fix the problem. This approach also creates a large burden for the application engineering group because user inquiries need to be personally addressed. This approach can also be error prone because it relies on the manual application of debugging techniques to the fitting problems. Further, this approach relies on the experience level of the applications engineers and some engineers have more knowledge of certain CPLDs than others. Another disadvantage of this approach is that fitting errors can make the fitter software look inadequate to the user, and can cause stress to users who do not fully understand the architecture of CPLDs.
Accordingly, what is needed is a system and method for proactively debugging fitting problems that can arise in the programming processes of programmable logic devices, such as CPLDs. What is needed further is an automatic system and method for proactively debugging fitting problems that also eliminate or minimize delay in the design cycle for users and also that can be used to reduce the workload burden on the application engineering groups of CPLD or other PLD suppliers. These and other advantages of the present invention not specifically recited above will become clear within discussions of the present invention presented herein.
A method and system are described herein for automatically proactively debugging fitting problems in programmable devices. Automatic fitters are computer programs that place and route circuit resources within a programmable device, e.g., a complex programmable logic device (CPLD) to determine the resources used and timing for a given integrated circuit (IC) or PLD design. Upon a fitting failure for an IC or PLD design, an embodiment of the present invention first identifies any specific architectural information, if any, causing the failure and may advise the user including solution recommendations. Second, an embodiment of the invention obtains a larger device (includes larger virtual device) having the same pin package as the original design choice, if available, and performs a second fitting on the IC or PLD design but using this larger device.
If this fits properly, then the resulting pin assignment is fixed and a third fitting may be performed on the smaller device with the fixed pin assignment. If this fails, this frequently can be used to draw further information from the fitting process and any further architectural violations may be identified and solution recommendations are given to the user. If there are no larger devices that can be used with the IC or PLD design and/or the third fitting does not obtain a proper result, then an embodiment of the invention uses virtual devices. If this does not work, then an embodiment of the present invention may determine if specific named pins are failing to fit. If these pins are identified, and the user has not locked them down, then they are allowed to float and fitting is performed once more. If no solution can be reached after the above attempts, then the invention may inform the user that technical support is required and a history of the fitting attempts is recorded. This can automatically be provided to the applications hotline by an automatic email from the fitter software. A programming file may be generated upon a successful fit.
More specifically, an embodiment of the present invention includes a method of debugging fitting problems comprising the steps of: a) in response to an integrated circuit (PLD) design failing a first fitting on a first programmable device, automatically selecting a second programmable device having more resources than the first programmable device but having a same pin package; b) automatically performing a second fitting of the PLD design on the second programmable device which, if successful, yields a determined pin assignment; and c) automatically performing a third fitting of the PLD design on the first programmable device and constrained by the determined pin assignment. Embodiments include the above and further comprising the steps of: automatically reporting any discovered architectural violations and their suggested solutions; provided the third fitting generates fitting problems, identifying select pins that fail fitting; and provided the select pins that fail fitting are not locked down, automatically performing a fourth fitting of the PLD design on the first programmable device and constrained by the determined pin assignment but floating the select pins that fail fitting.
Embodiments include the above and further comprising the steps of: provided the third fitting generates fitting problems, identifying any newly discovered architectural violations; and automatically reporting the any newly discovered architectural violations and their suggested solutions. Embodiments also include a system implemented in accordance with the above.